IDT5T915 Datasheet | Integrated Device Technology

IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE .. 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER™ Features : - - - - - - - - DESCRIPTION: Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion < 300ps (max) High speed propagation delay < 2ns (max) Up to 250MHz operation Very low CMOS power levels Hot insertable and over-voltage tolerant inputs 3-level inputs for selectable interface Selectable HSTL, e HSTL, 1.8V / 2.5V LVTTL, or LVEPECL input interface - Selectable differential or single-ended inputs and five differential outputs - 2.5V VDD - Available in TSSOP package The IDT5T915 2.5V differential (DDR) clock buffer is a user-selectable single-ended or differential input to five differential outputs built on advanced metal CMOS technology. The differential clock buffer fanout from a single or differential input to five differential or single-ended outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T915 can act as a translator from a differential HSTL, e HSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, e HSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The IDT5T915 true or plementary outputs can be asynchronously enabled/disabled. Multiple power and grounds reduce noise. - Clock and signal distribution APPLICATIONS: FUNCTIONAL BLOCK DIAGRAM Tx S GL G(+) OUTPUT CONTROL Q1 OUTPUT CONTROL Q1 OUTPUT CONTROL Q2 Rx S A A/VREF OUTPUT CONTROL Q2 OUTPUT...