IDT5T915 Description
The differential clock buffer fanout from a single or differential input to five differential or single-ended outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T915 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is...
IDT5T915 Key Features
- Selectable differential or single-ended inputs and five differential outputs
- 2.5V VDD
- Available in TSSOP package
- Clock and signal distribution