IDT6178S Datasheet | Integrated Device Technology

IDT6178S CMOS Static RAM 16K (4K x 4-BIT) CACHE-TAG RAM MILITARY AND MERCIAL TEMPERATURE RANGE CMOS Static RAM 16K (4K x 4-BIT) CACHE-TAG RAM Integrated Device Technology, Inc. Features : - High-speed Address to MATCH Valid time - Military: 12/15/20/25ns - mercial: 10/12/15/20/25ns (max.) - High-speed Address Access time - Military: 12/15/20/25ns - mercial: 10/12/15/20/25ns (max.) - Low-power consumption - IDT6178S Active: 300m W (typ.) - Produced with advanced CMOS high-performance technology - Input and output TTL-patible - Standard 22-pin Plastic or Ceramic DIP, 24-pin SOJ - Military product 100% pliant to MIL-STD-883, Class B DESCRIPTION: The IDT6178 is a high-speed cache address parator sub-system consisting of a 16,384-bit Static RAM organized as 4K x 4. Cycle Time and Address to MATCH Valid are equal. The IDT6178 Features an onboard 4-bit parator that pares RAM contents and current input data. The result is an active HIGH on the MATCH pin. The MATCH pins of several IDT6178s can be handed together to provide enabling or acknowledging signals to the data cache or processor. The IDT6178 is fabricated using IDT’s high-performance, high-reliability CMOS technology. Address to MATCH and Data to MATCH times are as fast as 10ns. All inputs and outputs of the IDT6178 are TTL-patible and the device operates from a single 5V supply. The IDT6178 is packaged in either a 22-pin, 300-mil Plastic or Ceramic DIP package or 24-pin SOJ. Military grade product is manufactured in pliance with latest revision of MILSTD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. FUNCTIONAL BLOCK DIAGRAM A0 ADDRESS DECODE A11 16,384-BIT MEMORY ARRAY VCC GND I/O0 - I/O3 CONTROL I/O WE OE CLR CONTROL CLEAR MEMORY ARRAY PARATOR MATCH...