IDT6178S Overview
The IDT6178 is a high-speed cache address parator sub-system consisting of a 16,384-bit StaticRAM organized as 4K x 4. Cycle Time and Address to MATCH Valid are equal.
IDT6178S Key Features
- High-speed Address to MATCH Valid time
- Military: 12/15/20/25ns
- mercial: 10/12/15/20/25ns (max.)
- High-speed Address Access time
- Military: 12/15/20/25ns
- mercial: 10/12/15/20/25ns (max.)
- Low-power consumption
- IDT6178S Active: 300mW (typ.)
- Produced with advanced CMOS high-performance technology
- Input and output TTL-patible