Datasheet Details
| Part number | IDT70V28L |
|---|---|
| Manufacturer | Integrated Device Technology |
| File Size | 194.72 KB |
| Description | HIGH-SPEED 3.3V 64K x 16 DUAL-PORT STATIC RAM |
| Download | IDT70V28L Download (PDF) |
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Download the IDT70V28L datasheet PDF. This datasheet also includes the IDT-70V variant, as both parts are published together in a single manufacturer document.
| Part number | IDT70V28L |
|---|---|
| Manufacturer | Integrated Device Technology |
| File Size | 194.72 KB |
| Description | HIGH-SPEED 3.3V 64K x 16 DUAL-PORT STATIC RAM |
| Download | IDT70V28L Download (PDF) |
|
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The IDT70V28 is a high-speed 64K x 16 Dual-Port Static RAM.
The IDT70V28 is designed to be used as a stand-alone 1024K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word system.
Using the IDT MASTER/SLAVE Dua
HIGH-SPEED 3.3V 64K x 16 DUAL-PORT STATIC RAM .eatures True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 15/20ns (max.) – Industrial: 20ns (max.) Low-power operation – IDT70V28L Active: 440mW (typ.) Standby: 660µW (typ.) Dual chip enables allow for depth expansion without external logic IDT70V28 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device x x x x IDT70V28L x x x x x x x x x x M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility LVTTL-compatible, single 3.3V (±0.3V) power supply Available in a 100-pin TQFP Industrial temperature range (–40°C to +85°C) is available for selected speeds .unctional Block Diagram R/WL UBL CE0L CE1L OEL LBL R/WR UBR CE0R CE1R OER LBR I/O 8-15L I/O 0-7L BUSYL (1,2) A15L A0L 64Kx16 MEMORY ARRAY 70V28 16 16 I/O8-15R I/O Control I/O Control I/O0-7R BUSYR A15R A0R (1,2) Address Decoder Address Decoder CE0L CE1L OEL R/WL SEML ARBITRATION INTERRUPT SEMAPHORE LOGIC CE0R CE1R OER R/WR SEMR (2) INTR 4849 drw 01 M/S NOTES: 1.
BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2.
| Part Number | Description |
|---|---|
| IDT70V24L | HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM |
| IDT70V24S | HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM |
| IDT70V25L | HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM |
| IDT70V25S | HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM |
| IDT70V261L | HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM |
| IDT70V261S | HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM |
| IDT70V26L | HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM |
| IDT70V26S | HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM |
| IDT70V27L | HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM |
| IDT70V27S | HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM |