IDT71B74 Overview
The IDT71B74 is a high-speed cache address parator subsystem consisting of a 65,536-bit static RAM organized as 8K x 8 and an 8-bit parator. A single IDT71B74 can map 8K cache words into a 2 megabyte address space by using the 21 bits of address organized with the 13 LSBs for the cache address bits and the 8 higher bits for cache data bits. Two IDT71B74s can be bined to provide 29 bits of address parison, etc.
IDT71B74 Key Features
- High-speed address to MATCH parison time
- mercial: 8/10/12/15/20ns (max.)
- High-speed address access time
- mercial: 8/10/12/15/20ns (max.)
- High-speed chip select access time
- mercial: 6/7/8/10ns (max.)
- Power-ON Reset Capability
- Low power consumption
- 830mW (typ.) for 12ns parts
- 880mW (typ.) for 10ns parts