IDT72V3624 Datasheet | Integrated Device Technology

.. 3.3 VOLT CMOS Sync Bi FIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 - - - - - IDT72V3624 IDT72V3634 IDT72V3644 .EATURES: - - - - - - Memory storage capacity: IDT72V3624- 256 x 36 x 2 IDT72V3634- 512 x 36 x 2 IDT72V3644- 1,024 x 36 x 2 Clock frequencies up to 100 MHz (6.5ns access time) Two independent clocked FIFOs buffering data in opposite directions Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags functions) or First Word Fall Through Timing (using ORA, ORB, IRA, and IRB flag functions) Programmable Almost-Empty and Almost-Full flags; each has three default offsets (8, 16 and 64) Serial or parallel programming of partial flags - - - - Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte) Big- or Little-Endian format for word and byte bus sizes Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings Mailbox bypass registers for each FIFO Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Auto power down minimizes power dissipation Available in space saving 128-pin Thin Quad Flatpack (TQFP) Pin and functionally patible version of the 5V operating IDT723624/723634/723644 Industrial temperature range (- 40°C to +85°C) is available .UNCTIONAL BLOCK DIAGRAM MBF1 Mail 1 Register Output Bus Matching Input Register Output Register CLKA CSA W/RA ENA MBA MRS1 PRS1 Port-A Control Logic RAM ARRAY 256 x 36 512 x 36 1,024 x 36 FIFO1, Mail1 Reset Logic Write Pointer Read Pointer Status Flag Logic EFB/ORB AEB FFA/IRA AFA SPM FS0/SD FS1/SEN A0-A35 EFA/ORA AEA FIFO1 Programmable Flag Offset Registers 10 FIFO2 Timing Mode FWFT B0-B35 Status Flag Logic Read Pointer Write...