IDT74LVC373A Datasheet | Integrated Device Technology

.. IDT74LVC373A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200p F, R = 0) - VCC = 3.3V ± 0.3V, Normal Range - VCC = 2.7V to 3.6V, Extended Range - CMOS power levels (0.4µ W typ. static) - Rail-to-rail output swing for increased noise margin - All inputs, outputs, and I/O are 5V tolerant - Supports hot insertion - Available in SOIC, SSOP, QSOP, and TSSOP packages Features : DESCRIPTION: DRIVE Features : - High Output Drivers: ±24m A - Reduced system switching noise APPLICATIONS: - 5V and 3.3V mixed voltage systems - Data munication and telemunication systems The LVC373A Octal transparent D-type latch is built using advanced dual metal CMOS technology. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high- impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup ponents. OE does not affect the internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the highimpedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system...