IDT88P8344 Description
The IDT88P8344 is a SPI (System Packet Interface) Exchange with four SPI3 interfaces and one SPI-4 interface. The data that enter on the low speed interface (SPI-3) are mapped to logical identifiers (LIDs) and enqueued for transmission over the high speed interface (SPI-4). The data that enter on the high speed interface (SPI-4) are mapped to logical identifiers (LIDs) and enqueued for transmission over a low speed...
IDT88P8344 Key Features
- Low speed to high speed SPI exchange device
- Logical port (LP) mapping (SPI-3 <-> SPI-4) tables per direction
- Per LP configurable memory allocation
- Maskable interrupts for fatal errors
- Fragment and burst length configurable per interface: min 16 bytes, max 256 bytes
- Standard Interfaces
- Four OIF SPI-3: 8 or 32 bit, 19.44-133 MHz, 256 address range, 64 concurrently active LPs per interface
- One OIF SPI-4 phase 2: 80
- 400 MHz, 256 address range, 256 concurrently active LPs
- SPI-4 FIFO status channel options