IDTCV107E Datasheet PDF - Integrated Device Technology CLOCK GENERATOR FOR DESKTOP PC PLATFORMS Specs

IDTCV107E - CLOCK GENERATOR FOR DESKTOP PC PLATFORMS

Datasheet Summary

Description

KEY SPECIFICATION: CPU/SRC CLK cycle to cycle jitter < 125ps SATA CLK cycle to cycle jitter < 125ps PCI CLK cycle to cycle jitter < 250ps Static PLL frequency divide error as low as 36 ppm FUNCTIONAL BLOCK DIAGRAM DataSheet4U.com PLL1 SSC EasyN Programming

Features

4 PLL architecture Linear frequency programming Independent frequency programming and SSC control Band-gap circuit for differential output High power-noise rejection ratio 66MHz to 533MHz CPU frequency VCO frequency up to 1.1G Support index block read/write, single cycle index block read Programmable REF, 3V66, PCI, 48MHz I/O drive strength Programmable 3V66 and PCI Skew Available in S.

Datasheet Details

Part number	IDTCV107E
Manufacturer	Integrated Device Technology
File Size	215.39 KB
Description	CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
Datasheet	IDTCV107E Datasheet
Additional preview pages of the IDTCV107E datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com IDTCV107E CLOCK GENERATOR FOR DESKTOP PC PLATFORMS COMMERCIAL TEMPERATURE RANGE CLOCK GENERATOR FOR DESKTOP PC PLATFORMS IDTCV107E FEATURES: • • • • • • • • • • • 4 PLL architecture Linear frequency programming Independent frequency programming and SSC control Band-gap circuit for differential output High power-noise rejection ratio 66MHz to 533MHz CPU frequency VCO frequency up to 1.1G Support index block read/write, single cycle index block read Programmable REF, 3V66, PCI, 48MHz I/O drive strength Programmable 3V66 and PCI Skew Available in SSOP package IDTCV107E is a 48 pin clock generation device for desktop PC platforms. This chip incorporates four PLLs to allow independent generation of CPU, AGP/ PCI, SRC, and 48MHz clocks.

Published: Oct 11, 2006 |