IDTVP386 Datasheet | Integrated Device Technology

Description The VP386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.8 Gbps throughput or 350 Mbytes per second. This chip is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces through very low-swing LVDS signals. Features - Wide clock frequency range from 20 MHz to 100 MHz - Pin patible with the National DS90CF386, THine THC63LVDF84, TISN65LVDS94 - Converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data - Fully spread spectrum patible - LVDS voltage swing of 350 m V for low EMI - On-chip PLL requires no external ponents - Low-power CMOS design - Falling edge clock triggered outputs - Power-down control function - patible with TIA/EIA-644 LVDS standards - Packaged in a 56-pin TSSOP (Pb free available) Rx OUT0...27 Block Diagram Rx IN0+ Rx IN0Rx IN1+ Rx IN1Rx IN2+ Rx IN2Rx IN3+ Rx IN3- Rx CLKIN+ Rx CLKIN- PWRDWN LVDS to TTL De-serializer 8 RED 8 GREEN 8 BLUE HSYNC VSYNC DATA ENABLE CONTROL Rx CLKOUT VP386 8/28-BIT LVDS RECEIVER FOR VIDEO 7129/3 IDTVP386 8/28-BIT LVDS RECEIVER FOR...