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IDT23S09E Datasheet 3.3v Zero Delay Clock Buffer

Manufacturer: Integrated Device Technology

Overview: IDT23S09E 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES www.DataSheet4U.com 3.

General Description

: IDT23S09E • Phase-Lock Loop Clock Distribution • 10MHz to 200MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each output bank • Output Skew < 250ps • Low jitter <200 ps cycle-to-cycle • IDT23S09E-1 for Standard Drive • IDT23S09E-1H for High Drive • No external RC network required • Operates at 3.3V VDD • Spread spectrum compatible • Available in SOIC and TSSOP packages The IDT23S09E is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications.

The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 200MHz.

The IDT23S09E is a 16-pin version of the IDT23S05E.

IDT23S09E Distributor