IDT23S09 Overview
The zero delay is achieved by aligning the phase between the ining clock and the output clock, operable within the range of 10 to 133MHz. The IDT23S09 is a 16-pin version of the IDT23S05. The IDT23S09 accepts one reference input, and drives two banks of four low skew clocks.
IDT23S09 Key Features
- Phase-Lock Loop Clock Distribution
- 10MHz to 133MHz operating frequency
- Distributes one clock input to one bank of five and one bank of four outputs
- Separate output enable for each output bank
- Output Skew < 250ps
- Low jitter <200 ps cycle-to-cycle
- IDT23S09-1 for Standard Drive
- IDT23S09-1H for High Drive
- No external RC network required
- Operates at 3.3V VDD
