IDT23S09 Datasheet
IDT23S09 Datasheet (Integrated Device)
Integrated Device
IDT23S09 • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each .
DESCRIPTION:
IDT23S09
* Phase-Lock Loop Clock Distribution
* 10MHz to 133MHz operating frequency
* Distributes one clock input to one bank of five and one bank of four outputs
* Separate output enable for each output bank
* Output Skew < 250ps
* Low jitter <200 ps cycle-to-cycle
* IDT23S09-1 for .
IDT23S09 Datasheet (Renesas)
Renesas
The IDT23S09 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming .
* Phase-Lock Loop Clock Distribution
* 10MHz to 133MHz operating frequency
* Distributes one clock input to one bank of five and one bank of
four outputs
* Separate output enable for each output bank
* Output Skew < 250ps
* Low jitter <200 ps cycle-to-cycle
* IDT23S09-1 for Standard Drive
* IDT23S0.