IDT23S08T Overview
It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the ining clock and the output clock, operable within the range of 10 to 133MHz. The IDT23S08T has two banks of four outputs each that are controlled via two select addresses.
IDT23S08T Applications
- Distributes one clock input to two banks of four outputs
- Separate output enable for each output bank
- External feedback (FBK) pin is used to synchronize the outputs to the clock input
