IDT23S08 Overview
IDT23S08 Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency Distributes one clock input to two banks of four outputs Separate output enable for each output bank External feedback (FBK) pin is used to synchronize the outputs to the clock input Output Skew <200 ps Low jitter <200 ps cycle-to-cycle 1x, 2x, 4x output options (see table): It is designed to address...
IDT23S08 Applications
- Distributes one clock input to two banks of four outputs
- Separate output enable for each output bank
- External feedback (FBK) pin is used to synchronize the outputs to the clock input
