QS5917T Datasheet | Integrated Device Technology

.Data Sheet.co.kr QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER Features : - - - - - - - - - - - - - QS5917T 5V operation 2x Q output, Q/2 output, Q output Outputs tri-state while RST low Internal loop filter RC network Low noise TTL level outputs < 500ps output skew, Q0-Q4 PLL disable feature for low frequency testing Balanced Drive Outputs ± 24m A 132MHz maximum frequency (2x Q output) Functional equivalent to Motorola MC88915 ESD > 2000V Latch-up > - 300m A Available in QSOP and PLCC packages DESCRIPTION The QS5917T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: Q0-Q4, 2x Q, Q/2, Q5. Careful layout and design insures < 500ps skew between the Q0-Q4, and Q/2 outputs. The QS5917T includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external ponents. In addition, TTL level outputs reduce clock signal noise. Various binations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The VCO can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The LOCK output asserts to indicate when phase lock has been achieved. The QS5917T is designed for use in high-performance workstations, multi-board puters, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. For more information on PLL clock driver products, see Application Note AN-227. FUNCTIONAL BLOCK DIAGRAM REF_SEL LOCK FEEDBACK PLL_EN FREQ_SEL SYNC0 SYNC1 RST 0 0 1 PHASE DETECTOR LOOP FILTER 1 /2 Q/2 Q5 Q4 Q3...