QS5919T Datasheet | Integrated Device Technology

.Data Sheet.co.kr QS5919T LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER Features : - - - - - - - - - - - - 5V operation Low noise TTL level outputs < 350ps output skew, Q0- Q4 2x Q output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC network Functional equivalent to Motorola MC88915 Positive or negative edge synchronization (PE) Balanced drive outputs ±24m A 160MHz maximum frequency (2x Q output) Available in QSOP and PLCC packages DESCRIPTION The QS5919T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2x Q, Q 0-Q4, Q5, Q/2. Careful layout and design ensure < 350ps skew between the Q0-Q4, and Q/2 outputs. The QS5919T includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external ponents. Various binations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The LOCK output asserts to indicate when phase lock has been achieved. The QS5919T is designed for use in highperformance workstations, multi-board puters, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. For more information on PLL clock driver products, see Application Note AN-227. FUNCTIONAL BLOCK DIAGRAM REF_SEL LO CK SYNC 0 SYNC 1 O E/RST 0 0 1 PH A S E D ETEC TO R LO O P FIL TER 1 FEE DBACK PLL_E N FREQ _SEL /2 Q /2 Q5 Q4 Q3 Q2 Q1 Q0 2x...