QS5919T - LOW SKEW TTL PLL CLOCK DRIVER

Product Overview

Integrated Device Technology

Part number	QS5919T
Manufacturer	Integrated Device Technology
File Size	163.47 KB
Description	LOW SKEW TTL PLL CLOCK DRIVER
Datasheet	QS5919T Datasheet
Additional preview pages of the QS5919T datasheet.

The QS5919T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs.

Eight outputs are available: 2xQ, Q 0-Q4, Q5, Q/2.

Careful layout and design ensure < 350ps skew between the Q0-Q4, and Q/2 outputs.

5V operation Low noise TTL level outputs < 350ps output skew, Q0.
Q4 2xQ output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC network Functional equivalent to Motorola MC88915 Positive or negative edge synchronization (PE) Balanced drive outputs ±24mA 160MHz maximum frequ.

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Published: Sep 23, 2011 |