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IS61SPD25632T - 256K x 32/ 256K x 36/ 512K x 18 SYNCHRONOUS PIPELINE/ DOUBLE-CYCLE DESELECT STATIC RAM

General Description

IS61LPD25632, IS61LPD25636, and IS61LPD51218 are high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors.

Key Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Pentium™ or linear burst sequence control using MODE input.
  • Three chip enable option for simple depth expansion and address pipelining.
  • Common data inputs and data outputs.
  • JEDEC 100-Pin TQFP and 119-pin PBGA package.
  • Single +3.3V, +10%,.
  • 5% power supply.
  • Power-down snooze.

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Datasheet Details

Part number IS61SPD25632T
Manufacturer ISSI (now Infineon)
File Size 154.12 KB
Description 256K x 32/ 256K x 36/ 512K x 18 SYNCHRONOUS PIPELINE/ DOUBLE-CYCLE DESELECT STATIC RAM
Datasheet download datasheet IS61SPD25632T Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D 256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, DOUBLE-CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • JEDEC 100-Pin TQFP and 119-pin PBGA package • Single +3.3V, +10%, –5% power supply • Power-down snooze mode • 3.3V I/O For SPD • 2.