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42S16100 - IS42S16100

Description

organized as a 524,288-word x 16-bit x 2-bank for improved performance.

The synchronous DRAMs achieve high-speed data transfer using pipeline architecture.

All inputs and outputs signals refer to the rising edge of the clock input.

Features

  • Clock frequency: 200, 166, 143 MHz.
  • Fully synchronous; all signals referenced to a positive clock edge.
  • Two banks can be operated simultaneously and independently.
  • Dual internal bank controlled by A11 (bank select).
  • Single 3.3V power supply.
  • LVTTL interface.
  • Programmable burst length.
  • (1, 2, 4, 8, full page).
  • Programmable burst sequence: Sequential/Interleave.
  • 2048 refresh cycles every 32 ms.

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Other Datasheets by ISSI (now Infineon)

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Full PDF Text Transcription

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IS42S16100 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM FEBRUARY 2008 FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks can be operated simultaneously and independently • Dual internal bank controlled by A11 (bank select) • Single 3.
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