42S16100 Datasheet | ISSI

FEATURES - Clock frequency: 200, 166, 143 MHz - Fully synchronous; all signals referenced to a positive clock edge - Two banks can be operated simultaneously and independently - Dual internal bank controlled by A11 (bank select) - Single 3.3V power supply - LVTTL interface - Programmable burst length - (1, 2, 4, 8, full page) - Programmable burst sequence: Sequential/Interleave - 2048 refresh cycles every 32 ms - Random column address every clock cycle - Programmable CAS latency (2, 3 clocks) - Burst read/write and burst read/single write operations capability - Burst termination by burst stop and precharge mand - Byte controlled by LDQM and UDQM - Packages 400-mil 50-pin TSOP-II and 60-ball BGA - Lead-free package option - Available in Industrial Temperature DESCRIPTION ISSI’s 16Mb Synchronous DRAM IS42S16100 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. PIN CONFIGURATIONS 50-Pin TSOP (Type II) VDD DQ0 DQ1 GNDQ DQ2 DQ3 VDDQ DQ4 DQ5 GNDQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 GND 49 DQ15 48 IDQ14 47 GNDQ 46 DQ13 45 DQ12 44 VDDQ 43 DQ11 42 DQ10 41 GNDQ 40 DQ9 39 DQ8 38 VDDQ 37 NC 36 UDQM 35 CLK 34 CKE 33 NC 32 A9 31 A8 30 A7 29 A6 28 A5 27 A4 26 GND PIN DESCRIPTIONS A0-A11 Address Input A0-A10 Row Address Input A11 Bank Select Address A0-A7 Column Address Input DQ0 to DQ15 Data DQ System Clock...