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IS41C85125A - 512K x 8 (4-MBIT) DYNAMIC RAM

General Description

The ISSI IS41C85125A and IS41LV85125A are 512,288 x 8bit high-performance CMOS Dynamic Random Access Memories.

Fast Page Mode allows 1024 random accesses within a single row with access cycle time as short as 12 ns per 8-bit word.

Key Features

  • Fast access and cycle time TTL compatible inputs and outputs Refresh Interval: 1024 cycles/16 ms Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden.
  • JEDEC standard pinout.
  • Single power supply: -- 5V ± 10% (IS41C85125A) -- 3.3V ± 10% (IS41LV85125A).
  • Lead-free available ISSI APRIL 2005 ® www. DataSheet4U. com.

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📁 Similar Datasheet

Part Number Description Manufacturer
IS41C8512 512K x 8 (4-MBIT) DYNAMIC RAM Integrated Circuit Solution
IS41C16128 128K x 16 (2-MBIT) DYNAMIC RAM ISSI
IS41C16256 256K x 16 (4-MBIT) DYNAMIC RAM ISSI
IS41C16257 256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE Integrated Silicon Solution Inc
IS41LV16256 256K x 16 (4-MBIT) DYNAMIC RAM ISSI

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS41C85125 512K x 8 (4-MBIT) DYNAMIC RAM
IS41C85120 512K x 8 (4-MBIT) DYNAMIC RAM
IS41C85120A 512K x 8 (4-MBIT) DYNAMIC RAM
IS41C8200 2M x 8 (16-MBIT) DYNAMIC RAM
IS41C8205 2M x 8 (16-MBIT) DYNAMIC RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS41C85125A IS41LV85125A 512K x 8 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE FEATURES • • • • Fast access and cycle time TTL compatible inputs and outputs Refresh Interval: 1024 cycles/16 ms Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden • JEDEC standard pinout • Single power supply: -- 5V ± 10% (IS41C85125A) -- 3.3V ± 10% (IS41LV85125A) • Lead-free available ISSI APRIL 2005 ® www.DataSheet4U.com DESCRIPTION The ISSI IS41C85125A and IS41LV85125A are 512,288 x 8bit high-performance CMOS Dynamic Random Access Memories. Fast Page Mode allows 1024 random accesses within a single row with access cycle time as short as 12 ns per 8-bit word.