Description
A0-A12
Row Address Input
A0-A8
Column Address Input
BA0, BA1
Bank Select Address
DQ0 to DQ15 Data I/O
CLK
System Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
WE DQML DQMH Vdd Vss Vddq Vssq
Features
- Clock frequency: 166, 143, 133 MHz.
- Fully synchronous; all signals referenced to a positive clock edge.
- Internal bank for hiding row access/precharge.
- Power supply
IS42S16160
Vdd Vddq 3.3V 3.3V.
- LVTTL interface.
- Programmable burst length.
- (1, 2, 4, 8, full page).
- Programmable burst sequence: Sequential/Interleave.
- Auto Refresh (CBR).
- Self Refresh.
- 8K refresh cyc.