Datasheet Summary
16Meg x16
256-MBIT SYNCHRONOUS DRAM
SEPTEMBER 2009
Features
- Clock frequency: 166, 143, 133 MHz
- Fully synchronous; all signals referenced to a positive clock edge
- Internal bank for hiding row access/precharge
- Power supply
Vdd Vddq 3.3V 3.3V
- LVTTL interface
- Programmable burst length
- (1, 2, 4, 8, full page)
- Programmable burst sequence: Sequential/Interleave
- Auto Refresh (CBR)
- Self Refresh
- 8K refresh cycles every 64 ms
- Random column address every clock cycle
- Programmable CAS latency (2, 3 clocks)
- Burst read/write and burst read/single write operations capability
- Burst termination by burst stop...
