IS42S32800B
Overview
The ISSI IS42S32800B is a high-speed CMOS configured as a quad 2M x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK). Each of the 2M x 32 bit banks is organized as 4096 rows by 512 columns by 32 and write accesses start at a selected locations in a programmed sequence.
- Concurrent auto precharge
- Clock rate:166/143 MHz
- Fully synchronous operation
- Internal pipelined architecture
- Four internal banks (2M x 32bit x 4bank)
- Programmable Mode -CAS#Latency:2 or 3 -Burst Length:1,2,4,8,or full page -Burst Type:interleaved or linear burst -Burst-Read-Single-Write
- Burst stop function
- Individual byte controlled by DQM0-3
- Auto Refresh and Self Refresh
- 4096 refresh cycles/64ms (15.6µs/row)
