Description
A0-A11 A0-A8 BA0, BA1 DQ0 to DQ31 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE DQM0-DQM3 Vdd Vss Vddq Vssq NC Wri
Features
- Clock frequency: 166, 143 MHz.
- Fully synchronous; all signals referenced to a positive clock edge.
- Internal bank for hiding row access/precharge.
- Single Power supply: 3.3V + 0.3V.
- LVTTL interface.
- Programmable burst length.
- (1, 2, 4, 8, full page).
- Programmable burst sequence: Sequential/Interleave.
- Auto Refresh (CBR).
- Self Refresh.
- 4096 refresh cycles every 16ms (A2 grade) or 64 ms (Com.