IS43R32400D Description
IS43R32400D 4Mx32 128Mb DDR SDRAM SEPTEMBER 2011.
IS43R32400D Key Features
- Double-data rate architecture; two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver
- DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs
- Differential clock inputs (CK and CK)
- DLL aligns DQ and DQS transitions with CK
- mands entered on each positive CK edge
- Four internal banks for concurrent operation
- Data Mask for write data. DM masks write data at both rising and falling edges of data strobe
- Burst Length: 2, 4 and 8
- Burst Type: Sequential and Interleave mode