IS49NLC96400A Datasheet PDF - Integrated Silicon Solution Common I/O RLDRAM 2 Memory Specs

IS49NLC96400A - Common I/O RLDRAM 2 Memory

Datasheet Summary

Description

1.1 576Mb (64Mx9) Common I/O BGA Ball-out (Top View) 1 2 3 4 5678 A VREF VSS VEXT VSS B VDD DNU3 DNU3 VSSQ C VTT DNU3 DNU3 VDDQ D A221 DNU3 DNU3 VSSQ E A21 DNU3 DNU3 VDDQ F A5 DNU3 DNU3 VSSQ G A8 A6 A7 VDD H BA2 A9 VSS VSS J NF2 NF2 VDD VDD K DK DK# VDD VDD

Features

533MHz DDR operation (1.067 Gb/s/pin data rate).
38.4Gb/s peak bandwidth (x36 at 533 MHz clock frequency).
Reduced cycle time (15ns at 533MHz).
32ms refresh (16K refresh for each bank; 128K refresh command must be issued in total each 32ms).
8 internal banks.
Non-multiplexed addresses (address multiplexing option available).
SRAM-type interface.
Programmable READ latency (RL), row cycle time, and burst sequence length.
Balanced READ and WRITE latenci.

Datasheet Details

Part number	IS49NLC96400A
Manufacturer	Integrated Silicon Solution
File Size	759.43 KB
Description	Common I/O RLDRAM 2 Memory
Datasheet	IS49NLC96400A Datasheet
Additional preview pages of the IS49NLC96400A datasheet.

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Full PDF Text Transcription

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IS49NLC96400A, IS49NLC18320A, IS49NLC36160A 576Mb (64Mbx9, 32Mbx18, 18Mbx36) Common I/O RLDRAM 2 Memory ADVANCED INFORMATION SEPTEMBER 2014 FEATURES  533MHz DDR operation (1.067 Gb/s/pin data rate)  38.4Gb/s peak bandwidth (x36 at 533 MHz clock frequency)  Reduced cycle time (15ns at 533MHz)  32ms refresh (16K refresh for each bank; 128K refresh command must be issued in total each 32ms)  8 internal banks  Non-multiplexed addresses (address multiplexing option available)  SRAM-type interface  Programmable READ latency (RL), row cycle time, and burst sequence length  Balanced READ and WRITE latencies in order to optimize data bus utilization  Data mask signals (DM) to mask signal of WRITE data; DM is sampled on both edges of DK.

Published: May 27, 2016 |