IS61DDP2B44M18A2 Datasheet PDF - Integrated Silicon Solution 72Mb DDR-IIP CIO SYNCHRONOUS SRAM Specs

IS61DDP2B44M18A2 - 72Mb DDR-IIP CIO SYNCHRONOUS SRAM

This page provides the datasheet information for the IS61DDP2B44M18A2, a member of the IS61DDP2B44M18A 72Mb DDR-IIP CIO SYNCHRONOUS SRAM family.

Datasheet Summary

Description

2Mx36 and 4Mx18 configuration available.

valid window.

Common I/O read and write ports.

operation.

Double Data Rate (DDR) interface for read and write input ports.

Datasheet Details

Part number	IS61DDP2B44M18A2
Manufacturer	Integrated Silicon Solution
File Size	932.69 KB
Description	72Mb DDR-IIP CIO SYNCHRONOUS SRAM
Datasheet	IS61DDP2B44M18A2 Datasheet
Additional preview pages of the IS61DDP2B44M18A2 datasheet.

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Full PDF Text Transcription

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IS61DDP2B44M18A/A1/A2 IS61DDP2B42M36A/A1/A2 4Mx18, 2Mx36 72Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM (2.0 Cycle Read Latency) NOVEMBER 2014 FEATURES DESCRIPTION  2Mx36 and 4Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.0 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5V to 1.8V VDDQ, used with 0.75 to 0.9V VREF.

Published: Jul 25, 2016 |