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IS61DDPB22M36 - DDR-IIP (Burst of 2) CIO Synchronous SRAMs

Download the IS61DDPB22M36 datasheet PDF. This datasheet also covers the IS61DDPB24M18 variant, as both devices belong to the same ddr-iip (burst of 2) cio synchronous srams family and are provided as variant models within a single manufacturer datasheet.

General Description

The 72Mb IS61DDPB22M36 and IS61DDPB24M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Key Features

  • 2M x 36 or 4M x 18.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Common data input/output bus.
  • Synchronous pipeline read with self-timed late write operation.
  • Double data rate (DDR-IIP) interface for read and write input ports.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K) for address and control registering at rising edges only.
  • Industrial te.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61DDPB24M18-IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61DDPB22M36C 72Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI
IS61DDPB22M36C1 72Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI
IS61DDPB22M36C2 72Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61DDPB22M36A 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB22M36A1 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB22M36A2 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB22M36B 72Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDPB22M36B1 72Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDPB22M36B2 72Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDPB22M18A 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB22M18A1 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB22M18A2 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB22M18B 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burs. t of 2) CIO Synchronous SRAMs (2.5 Cycle Read Latency) Advanced Information May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late write operation. • Double data rate (DDR-IIP) interface for read and write input ports. • Fixed 2-bit burst for read and write operations. • Clock stop support. • Two input clocks (K and K) for address and control registering at rising edges only. • Industrial temperature available upon request. • Two echo clocks (CQ and CQ) that are delivered simultaneously with data. • +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. • HSTL input and output levels.