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IS61DDPB22M36C2 - 72Mb DDR-IIP CIO SYNCHRONOUS SRAM

Download the IS61DDPB22M36C2 datasheet PDF. This datasheet also covers the IS61DDPB24M18C variant, as both devices belong to the same 72mb ddr-iip cio synchronous sram family and are provided as variant models within a single manufacturer datasheet.

General Description

at page 6 for each ODT option.

The 72Mb IS61DDPB22M36C/C1/C2 and IS61DDPB24M18 C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

Key Features

  • 2Mx36 and 4Mx18 configuration available.
  • Common I/O read and write ports.
  • Max. 567 MHz clock for high bandwidth.
  • Synchronous pipeline read with self-timed late write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • 2.5 cycle read latency.
  • Fixed 2-bit burst for read and write operations.
  • Two input clocks (K and K#) for address and control registering at rising edges only.
  • Two echo clocks (CQ and CQ#) that are delivere.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61DDPB24M18C-ISSI.pdf) that lists specifications for multiple related part numbers.

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61DDPB22M36C 72Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDPB22M36C1 72Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDPB24M18C 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB24M18C1 72Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDPB24M18C2 72Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B21M36C 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B21M36C1 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B21M36C2 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B22M18C 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B22M18C1 36Mb DDR-IIP CIO SYNCHRONOUS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61DDPB24M18C/C1/C2 IS61DDPB22M36C/C1/C2 4Mx18, 2Mx36 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (2.5 Cycle Read Latency) APRIL 2018 FEATURES  2Mx36 and 4Mx18 configuration available.  Common I/O read and write ports.  Max. 567 MHz clock for high bandwidth  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 cycle read latency.  Fixed 2-bit burst for read and write operations.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.  HSTL input and output interface.  Full data coherency.