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IS61NLP204836B - PIPELINE (NO WAIT) STATE BUS SRAM

General Description

The 72 Meg product family

Key Features

  • 100 percent bus utilization.
  • No wait cycles between Read and Write.
  • Internal self-timed write cycle.
  • Individual Byte Write Control.
  • Single R/W (Read/Write) control pin.
  • Clock controlled, registered address, data and control.
  • Interleaved or linear burst sequence control us- ing MODE input.
  • Three chip enables for simple depth expansion and address pipelining.
  • Power Down mode.
  • Common data inputs and data out.

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📁 Similar Datasheet

Part Number Description Manufacturer
IS61NLP25618A (IS61NVPxxxxxA) STATE BUS SRAM ISSI
IS61NLP25632 256K x 32/ 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM Integrated Silicon Solution Inc
IS61NLP25636 256K x 32/ 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM Integrated Silicon Solution Inc
IS61NLP25636A 9Mb STATE BUS SRAM ISSI
IS61NLP25636B 9Mb STATE BUS SRAM ISSI

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61NLP204818A 36Mb STATE BUS SRAM
IS61NLP102436A 36Mb STATE BUS SRAM
IS61NLP409618B PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLF204836B FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF409618B FLOW THROUGH (NO WAIT) STATE BUS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61NLP204836B/IS61NVP/NVVP204836B IS61NLP409618B/IS61NVP/NVVP409618B  2M x 36 and 4M x 18 JULY 2019 72Mb, PIPELINE 'NO WAIT' STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages • Power supply: NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVP: Vdd 2.5V (± 5%), Vddq 2.