IS61NLP204836B Datasheet | ISSI

IS61NLP204836B/IS61NVP/NVVP204836B IS61NLP409618B/IS61NVP/NVVP409618B  2M x 36 and 4M x 18 JULY 2019 72Mb, PIPELINE 'NO WAIT' STATE BUS SRAM Features - 100 percent bus utilization - No wait cycles between Read and Write - Internal self-timed write cycle - Individual Byte Write Control - Single R/W (Read/Write) control pin - Clock controlled, registered address, data and control - Interleaved or linear burst sequence control us- ing MODE input - Three chip enables for simple depth expansion and address pipelining - Power Down mode - mon data inputs and data outputs - CKE pin to enable clock and suspend operation - JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages - Power...