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IS61VPD51236A - 512K x 36/ 1024K x 18 18Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM

This page provides the datasheet information for the IS61VPD51236A, a member of the IS61LPD102418A 512K x 36/ 1024K x 18 18Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM family.

Datasheet Summary

Description

VPD102418A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.

Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Burst sequence control using MODE input.
  • Three chip enable option for simple depth expansion and address pipelining.
  • Common data inputs and data outputs.
  • Auto Power-down during deselect.
  • Double cycle deselect.
  • Snooze MODE for reduced-power standby.
  • JTAG Boundary Scan for.

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Datasheet preview – IS61VPD51236A

Datasheet Details

Part number IS61VPD51236A
Manufacturer Integrated Silicon Solution
File Size 251.04 KB
Description 512K x 36/ 1024K x 18 18Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM
Datasheet download datasheet IS61VPD51236A Datasheet
Additional preview pages of the IS61VPD51236A datasheet.

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Full PDF Text Transcription

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IS61VPD51236A IS61VPD102418A IS61LPD51236A IS61LPD102418A 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM www.DataSheet4U.com ISSI ® FEBRUARY 2006 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Double cycle deselect • Snooze MODE for reduced-power standby • JTAG Boundary Scan for PBGA package • Power Supply LPD: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% VPD: VDD 2.5V + 5%, VDDQ 2.
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