Description
80C186EA CORE ARCHITECTURE Bus Interface Unit Clock Generator 80C186EA PERIPHERAL ARCHITECTURE Interrupt Control Unit Timer Counter Unit DMA Control Unit Chip-Select Unit Refresh Control Unit Power Management 80C187 Interface (80C186EA Only) ONCE Test Mode DIFFERENCES BETWEEN THE 80C186XL AND THE 80C186EA Pinout patibility Operating Modes TTL vs CMOS Inputs Timing Specifications PACKAGE INFORMATION Prefix Identification Pin Descriptions 80C186EA Pinout PAGE 4 4 4 4 5 5 5 7 7 7 7 8 8 8 8 8 8 8 9 9 9 15 CONTENTS PACKAGE THERMAL SPECIFICATIONS ELECTRICAL SPECIFICATIONS PAGE 20 21 21 21 22 24 24 25 25 27 29 30 30 33 33 36 43 44 50 50 2 2 80C186EA 80C188EA 80L186EA 80L188EA NOTE Pin names in parentheses apply to the 80C186EA 80L188EA Figure 1 80C186EA 80C188EA 3 272432- 2 80C186EA 80C188EA 80L186EA 80L188EA INTRODUCTION Unless specifically noted all references to the 80C186EA apply to the 80C188EA 80L186EA and 80L188EA References to pins that differ between the 80C186EA 80L186EA and the 80C188EA 80L188EA are given in parentheses The ‘‘L’’ in the part number denotes low voltage operation Physically and functionally the ‘‘C’’ and ‘‘L’’ devices are identical The 80C186EA is the second product in a new generation of low-power high-integration microprocessors It enhances the existing 80C186XL family by offering new features and operating modes The 80C186EA is object code patible with the 80C186XL embedded processor The 80L186EA is t.
