Description
CORE ARCHITECTURE Bus Interface Unit Clock Generator 80C186EC PERIPHERAL ARCHITECTURE Interrupt Control Unit Timer Counter Unit Serial munications Unit Chip-Select Unit I O Port Unit Refresh Control Unit Power Management Unit 80C187 Interface (80C186EB Only) ONCE Test Mode PACKAGE INFORMATION Prefix Identification Pin Descriptions 80C186EB PINOUT PACKAGE THERMAL SPECIFICATIONS ELECTRICAL SPECIFICATIONS 4 4 4 4 5 5 5 7 7 7 7 7 7 7 8 8 8 14 22 23 23 CONTENTS Remended Connections DC SPECIFICATIONS ICC versus Frequency and Voltage PDTMR Pin Delay Calculation AC SPECIFICATIONS AC Characteristics 80C186EB25 AC Characteristics 80C186EB20 13 AC Characteristics 80L186EB16 Relative Timings Serial Port Mode 0 Timings AC TEST CONDITIONS AC TIMING WAVEFORMS DERATING CURVES RESET BUS CYCLE WAVEFORMS EXECUTION TIMINGS INSTRUCTION SET SUMMARY ERRATA REVISION HISTORY PAGE 23 24 27 27 28 28 30 32 36 37 38 38 41 42 45 52 53 59 59 2 80C186EB 80C188EB 80L186EB 80L188EB 272433 - 2 NOTE Pin names in parentheses apply to the 80C188EB 80L188EB Figure 1 80C186EB 80C188EB 3 80C186EB 80C188EB 80L186EB 80L188EB cept the queue status mode has been deleted and buffer interface control has been changed to ease system design timings An independent internal bus is used to allow munication between the BIU and internal peripherals INTRODUCTION Unless specifically noted all references to the 80C186EB apply to the 80C188EB 80L186EB and 80L188EB References to pins that differ between the 80C186EB 80L186EB and the 80C188EB 80L188EB are given in parentheses The ‘‘L’’ in the part number denotes low voltage operation Physically and functionally the ‘‘C’’ and ‘‘L’’ devices are identical The 80C186EB is the first product in a new generation of low-power high-inte.
