M28F008 Overview
M28F008 8 MBIT (1 MBIT x 8) FLASH MEMORY Y High-Density Symmetrically Blocked Architecture Sixteen 64 Kbyte Blocks Extended Cycling Capability 10K Block Erase Cycles Minimum 160K Block Erase Cycles per Chip Automated Byte Write and Block Erase mand User Interface Status Register System Performance Enhancements RY BY Status Output Erase Suspend Capability SRAM-patible Write Interface Y Very High-Performance Read 100...