82540EM
Overview
- PCI Bus - PCI Revision 2.3 support for 32-bit wide interface at 33 MHz and 66 MHz - Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands
- MAC Specific - Low-latency transmit and receive queues - IEEE 802.3x-compliant flow-control support with software-controllable thresholds - Caches up to 64 packet descriptors in a single burst - Programmable host memory receive buffers (256 B to 16 KB) and cache line size (16 B to 256 B) - Wide, optimized internal data path architecture - 64 KB configurable Transmit and Receive FIFO buffers
- PHY Specific - Integrated for 10/100/1000 Mb/s operation full and half duplex operation - IEEE 802.3ab Auto-Negotiation support - IEEE 802.3ab PHY compliance and compatibility. - State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation - Automatic detection of cable lengths and MDI vs. MDI-X cable at all speeds
- Host Off-Loading - Transmit and receive IP, TCP, and UDP checksum off-loading capabilities - Transmit TCP segmentation - Advanced packed filtering - Jumbo frame support up to 16 KB - IEEE 802.1q VLAN support with VLAN tag insertion, stripping and packet filtering for up to 4096 VLAN tags - Descriptor ring management hardware for transmit and receive - Interrupt coalescing (multiple packets per interrupt) - Jumbo frame support
- Manageability - Manageability features: SMB port, ASF 1.0, ACPI, Wake on LAN, and PXE - On-board SMB port - Compliance with PCI Power Management
- 1 and ACPI 2.0 register set compliant - SNMP and RMON statistic counters - SDG 3.0, WfM 2.0, and PC2001 compliance
- Additional Device - Four activity and link indication outputs that directly drive LEDs - JTAG (IEEE 1149.1) Test Access Port built in silicon - Internal PLL for clock generation can use a 25 MHz crystal - Program
