EP82562ET
Key Features
- IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface IEEE 802.3u Auto-Negotiation support Digital Adaptive Equalization control Link status interrupt capability XOR tree mode support 3-port LED support (speed, link and activity) 10BASE-T auto-polarity correction LAN Connect Interface * * * * * *
- Diagnostic loopback mode 1:1 transmit transformer ratio support Low power (less than 300 mW in active transmit mode) Reduced power in “unplugged mode” (less than 50 mW) Automatic detection of “unplugged mode” 3.3 V device 48-pin Shrink Small Outline Package Revision 1.4 November 2006 Free Datasheet Revision History Revision 0.55 0.6 Revision Date Sept. 1999 Nov. 1999 Initial release.
- Corrected Figure 4 “NRZ to MLT-3 Encoding Diagram on Pg. 11 to reflect correct signal transitions.
- Removed “10BASE-T Error Detection and Reporting” section since the 82562 does not do 10BASE-T error reporting.
- Updated bit 13 of Table 3 “Register 16 (10 Hexadecimal): PLC Status, Control and Address Data” to reflect correct values. Advance Information Datasheet release (Intel Secret).
- Modified Table 1 “82562ET Hardware Configuration” to add one row for XOR Tree and include column for comments.
- Updated the descrition of the Activity LED signal in Section 3.6, “LED Pins”.
- Revised Section 3.7, “Miscellaneous Control Pins” to reflect references to Table 1 “82562ET Hardware Configuration”.
- Updated Section 6.0, “Electrical and Timing Specifications”.
- Replaced diagrams in Section 7.1, “Package Information”. Advance Information Datasheet release (Intel Confidential).
