International C5001
This pin is the connection point for the devices Loop reference frequency. This may be either a CMOS 3.3 volt reference clock or the output of an external crystal.| Part No. | C5001 |
|---|---|
| Datasheet | C5001 Download |
| Manufacturer |  International |
| Description | Low Skew Muliple Frequency PCI Clock Generator |
| Buy | Stock & Price |
FEATURES
S S S S S S S S S S S S Produces PCI output clocks that are individually 2 selectable for 33.3 or 66.6 MHz under I C or strapping control. Separate output buffer power supply for reduced noise, crosstalk and jitter. input clock frequency standard 14.31818 MHz Output clocks frequency individually selectable via 2 I C or hardware bi-directional pin strapping. SSCG EMI reduction at 1.0% width 2 Individual clock disables via I C control All output clocks skewed within a 500 pS window Cycle to Cycle jitter ± 250 pS Output duty cycle is automatically 50% (±10%) adjusted Clock feed through mode and OE pins for logic testing Glitchless clock enabling and disabling transitions 28-pin TSSOP or SSOP package Output Enable logic Functionality Table OE CLK(0:9) PLL 1 (HIGH) Enabled Running 0 (LOW) Tri State Running Block Diagram XIN XOUT Reference Oscillator ÷1 ÷2 M U X Pin Configuration REFCLK0/S0 CLK1/S1 ÷1 ÷2 ÷1 ÷2 VDD CLK2/S2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16.
