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ACS630MS - Radiation Hardened EDAC

Description

The Intersil ACS630MS is a Radiation Hardened 16-bit parallel error detection and correction circuit.

It uses a modified Hamming code to generate a 6-bit check word from each 16-bit data word.

Features

  • Devices QML Qualified in Accordance with MIL-PRF-38535.
  • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96711 and Intersil’ QM Plan.
  • 1.25 Micron Radiation Hardened SOS CMOS.
  • Total Dose.
  • . . >300K RAD (Si).
  • Single Event Upset (SEU) Immunity: 10.
  • Dose Rate Survivability.
  • . >10.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ACS630MS January 1996 Radiation Hardened EDAC (Error Detection and Correction Circuit) Pinouts 28 PIN CERAMIC DUAL-IN-LINE, MIL-STD-1835 DESIGNATOR CDIP2-T28, LEAD FINISH C TOP VIEW DEF 1 DB0 2 DB1 3 DB2 4 DB3 5 DB4 6 DB5 7 DB6 8 28 VCC 27 SEF 26 S1 25 S0 24 CB0 23 CB1 22 CB2 21 CB3 20 CB4 19 CB5 18 DB15 17 DB14 16 DB13 15 DB12 Features • Devices QML Qualified in Accordance with MIL-PRF-38535 • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96711 and Intersil’ QM Plan • 1.25 Micron Radiation Hardened SOS CMOS • Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si) • Single Event Upset (SEU) Immunity: <1 x 10 (Typ) • Dose Rate Upset . . . . . . . . . . . . . . . . >10 • Dose Rate Survivability . . . . . . . . . . .
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