ACTS373MS Datasheet | Intersil

April 1995 Radiation Hardened Octal Transparent Latch, Three-State Pinouts 20 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C TOP VIEW OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 1 2 3 4 5 6 7 8 9 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 LE Features - 1.25 Micron Radiation Hardened SOS CMOS - Total Dose 300K RAD (Si) - Single Event Upset (SEU) Immunity <1 x 10-10 Errors/Bit-Day (Typ) - SEU LET Threshold >80 MEV-cm2/mg - Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse - Latch-Up Free Under Any Conditions - Military Temperature Range: -55o C to +125o C - Significant Power Reduction pared to ALSTTL Logic - DC Operating Voltage Range: 4.5V to 5.5V - Input Logic Levels - VIL = 0.8V Max - VIH = VCC/2V Min - Input Current ≤1µA at VOL, VOH GND 10 20 LEAD CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C TOP VIEW OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LE Description The Intersil ACTS373MS is a radiation hardened octal transparent latch with three-state outputs. The outputs are transparent to the inputs when the latch enable (LE) is high. When the LE goes low, the data is latched. When the Output Enable (OE) is high, the outputs are in the high impedance state. The latch operation is independent of the state of the output enable. The ACTS373MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radiation hardened, high-speed, CMOS/SOS Logic Family. Ordering Information PART NUMBER ACTS373DMSR ACTS373KMSR ACTS373D/Sample ACTS373K/Sample ACTS373HMSR TEMPERATURE RANGE -55o C to +125o C -55o C to +125o C +25o C +25o C +25o C SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample Sample Die PACKAGE 20 Lead SBDIP 20 Lead Ceramic Flatpack 20 Lead SBDIP 20 Lead Ceramic Flatpack Die Truth Table OE L L L L H LE H H L L X D H L I h X Q H L L H Z Functional Diagram 1 OF 8 (3, 4, 7, 8, 13,...