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CD4002BMS - CMOS NOR Gate

General Description

of “B” Series CMOS Device’s CD4001BMS TOP VIEW A 1 B 2 J=A+B 3 K=C+D 4 C 5 D 6 VSS 7 14 VDD 13 H 12 G 11 M = G + H 10 L = E + F 9 F 8 E NC = NO CONNECTION Description CD4000BMS CD4001BMS CD4002BMS CD4025BMS - Dual 3 Plus Inverter - Quad 2 Input - Dual 4 Input - Triple 3 Input CD4002BMS TOP VIEW J

Key Features

  • High-Voltage Types (20V Rating).
  • Propagation Delay Time = 60ns (typ. ) at CL = 50pF, VDD = 10V.
  • Buffered Inputs and Outputs.
  • Standard Symmetrical Output Characteristics.
  • 100% Tested for Maximum Quiescent Current at 20V.
  • 5V, 10V and 15V Parametric Ratings.
  • Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; 100nA at 18V and +25oC.
  • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V a.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CD4000BMS, CD4001BMS CD4002BMS, CD4025BMS November 1994 CMOS NOR Gate Pinouts CD4000BMS TOP VIEW NC 1 NC 2 A 3 B 4 C 5 H=A+B+C 6 VSS 7 14 VDD 13 F 12 E 11 D 10 K = D + E + F 9 L=G 8 G NC = NO CONNECTION Features • High-Voltage Types (20V Rating) • Propagation Delay Time = 60ns (typ.) at CL = 50pF, VDD = 10V • Buffered Inputs and Outputs • Standard Symmetrical Output Characteristics • 100% Tested for Maximum Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standards No.