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CD4019BMS - CMOS Quad AND/OR Select Gate

General Description

of ‘B’ Series CMOS Devices” Maximum Input Current of 1µa at 18V Over Full Package-Temperature Range; - 100nA at 18V and 25 oC Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V Functional Diagram Ka Kb VDD 16 9 15 14 Appl

Key Features

  • High Voltage Type (20V Rating).
  • Medium Speed Operation tPHL = tPLH = 60ns (typ. ) at CL = 50pF, VDD = 10V.
  • Standardized Symmetrical Output Characteristics.
  • 100% Tested for Quiescent Current at 20V.
  • 5V, 10V and 15V Parametric Ratings.
  • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CD4019BMS November 1994 CMOS Quad AND/OR Select Gate Pinout CD4019BMS TOP VIEW B4 1 A3 2 B3 3 A2 4 B2 5 A1 6 B1 7 VSS 8 16 VDD 15 A4 14 Kb 13 D4 = A4 Ka + B4 Kb 12 D3 = A3 Ka + B3 Kb 11 D2 = A2 Ka + B2 Kb 10 D1 = A1 Ka + B1 Kb 9 Ka Features • High Voltage Type (20V Rating) • Medium Speed Operation tPHL = tPLH = 60ns (typ.) at CL = 50pF, VDD = 10V • Standardized Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No.