CD4029BMS Datasheet PDF - Intersil Corporation CMOS Presettable Up/Down Counter Specs

CD4029BMS - CMOS Presettable Up/Down Counter

Datasheet Summary

Description

CD4029BMS consists of a four-stage binary or BCD-decade up/ down counter with provisions for look-ahead carry in both counting modes.

The inputs consist of a single CLOCK, CARRY-IN (CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals.

Features

High-Voltage Type (20V Rating).
Medium Speed Operation: 8MHz (Typ. ) at CL = 50pF and VDD - VSS = 10V.
Multi-Package Parallel Clocking for Synchronous High Speed Output Response or Ripple Clocking for Slow Clock Input Rise and Fall Times.
“Preset Enable” and Individual “Jam” Inputs Provided.
Binary or Decade Up/Down Counting.
BCD Outputs in Decade Mode.
100% Tested for Maximum Quiescent Current at 20V.
5V, 10V and 15V Parame.

Datasheet Details

Part number	CD4029BMS
Manufacturer	Intersil Corporation
File Size	124.65 KB
Description	CMOS Presettable Up/Down Counter
Datasheet	CD4029BMS Datasheet
Additional preview pages of the CD4029BMS datasheet.

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Full PDF Text Transcription

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CD4029BMS December 1992 CMOS Presettable Up/Down Counter Description CD4029BMS consists of a four-stage binary or BCD-decade up/ down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN (CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN and PRE-SET ENABLE signals are low.

Published: Mar 23, 2005 |