Datasheet Summary
December 1992
CMOS Dual 4-Bit Latch
Pinout
CD4508BMS TOP VIEW
RESET A 1 STROBE A 2 OUTPUT DISABLE A 3 D0A 4 Q0A 5 D1A 6 Q1A 7 D2A 8 Q2A 9 D3A 10 Q3A 11 VSS 12 24 VDD 23 Q3B 22 D3B 21 Q2B 20 D2B 19 Q1B 18 D1B 17 Q0B 16 D0B 15 OUTPUT DISABLE B 14 STROBE B 13 RESET B
Features
- High-Voltage Types (20-Volt Rating)
- Two Independent 4-Bit Latches
- Individual Master Reset for Each 4-Bit Latch
- 3-State Outputs with High-Impedance State for Bus Line Applications
- Medium-Speed Operation: tPHL = tPLH = 70nS (Typ.) at VDD = 10V and CL = 50pF
- 100% Tested for Quiescent Current at 20V
- 5V, 10V, and 15V Parametric Ratings
- Standardized, Symmetrical Output Characteristics
- Maximum...
