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CD4508BMS Datasheet CMOS Dual 4-bit Latch

Manufacturer: Intersil (now Renesas)

Overview: CD4508BMS December 1992 CMOS Dual 4-Bit Latch Pinout CD4508BMS TOP VIEW RESET A 1 STROBE A 2 OUTPUT DISABLE A 3 D0A 4 Q0A 5 D1A 6 Q1A 7 D2A 8 Q2A 9 D3A 10 Q3A 11 VSS 12 24 VDD 23 Q3B 22 D3B 21 Q2B 20 D2B 19 Q1B 18 D1B.

General Description

of ‘B’ Series CMOS Devices" Functional Diagram OUTPUT DISABLE D0A Q0A 4-BIT LATCH Q1A 3-STATE OUTUTS Q2A Q3A Applications • Buffer Storage • Holding Registers • Data Storage and Multiplexing D1A D2A D3A STROBE RESET OUTPUT DISABLE D0B D1B D2B D3B STROBE RESET Description CD4508BMS dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE controls.

With the STROBE line in the high state, the data on the "D" inputs appear at the corresponding "Q" outputs provided the DISABLE line is in the low state.

Changing the STROBE line to the low state locks the data into the latch.

Key Features

  • High-Voltage Types (20-Volt Rating).
  • Two Independent 4-Bit Latches.
  • Individual Master Reset for Each 4-Bit Latch.
  • 3-State Outputs with High-Impedance State for Bus Line.

CD4508BMS Distributor