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CD4512BMS - CMOS Dual 4-Bit Latch

General Description

of ‘B’ Series CMOS Devices" Functional Diagram 3-STATE DISABLE INHIBIT D0-1 D1-2 D2-3 CHANNELS INPUTS D3-4 D4-5 D5-6 D6-7 D7-9 A-11 SELECT CONTROL B-12 C-13 VDD = 16 VSS = 8 14 SELECT OUTPUT 10 15 Applications Digital Multiplexing Number-sequence Generation Signal Gat

Key Features

  • High-Voltage Types (20-Volt Rating).
  • 3-State Outputs.
  • Standardized, Symmetrical Output Characteristics.
  • 100% Tested for Quiescent Current at 20V.
  • 5V, 10V, and 15V Parametric Ratings.
  • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and 25oC.
  • Noise Margin (Full Package-Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V.
  • Meets all Requirements of JEDEC Tentative Sta.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CD4512BMS December 1992 CMOS Dual 4-Bit Latch Pinout CD4512BMS TOP VIEW D0 1 D1 2 D2 3 D3 4 D4 5 D5 6 D6 7 VSS 8 16 VDD 15 3-STATE DISABLE 14 SEL. OUTPUT 13 C 12 B 11 A 10 INHIBIT 9 D7 Features • High-Voltage Types (20-Volt Rating) • 3-State Outputs • Standardized, Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • 5V, 10V, and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and 25oC • Noise Margin (Full Package-Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets all Requirements of JEDEC Tentative Standard No.