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HI5634 - High Performance Programmable Phase-Locked Loop

Datasheet Summary

Description

PIN NO.

Features

  • Pixel Clock Frequencies up to 250MHz.
  • Very Low Jitter.
  • Digital Phase Adjustment (DPA) for Clock Outputs.
  • Balanced PECL Differential Outputs.
  • Single-Ended SSTL_3 Clock Outputs.
  • Double-Buffered PLL/DPA Control Registers.
  • Independent Software Reset for PLL/DPA.
  • External or Internal Loop Filter Selection.
  • Uses 3.3V Supply. Inputs are 5V Tolerant.
  • I2C-bus Serial Interface can Run at Either Low Speed (100kHz) o.

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Datasheet preview – HI5634

Datasheet Details

Part number HI5634
Manufacturer Intersil Corporation
File Size 160.77 KB
Description High Performance Programmable Phase-Locked Loop
Datasheet download datasheet HI5634 Datasheet
Additional preview pages of the HI5634 datasheet.

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Full PDF Text Transcription

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HI5634 PRELIMINARY Data Sheet May 1999 File Number 4745 High Performance Programmable Phase-Locked Loop for LCD Applications The HI5634 is a low cost but very high-performance frequency generator for line-locked and genlocked high resolution video applications. Utilizing an advanced low voltage CMOS mixed signal technology, the HI5634 is an effective clock solution for video projectors and displays at resolutions from VGA to beyond UXGA The HI5634 offers pixel clock outputs in both differential (to 250MHz) and single-ended (to 150MHz) formats. Digital phase adjustment circuitry allows user control of the pixel clock phase relative to the recovered sync signal. A second differential output at half the pixel clock rate enables deMUXing of multiplexed A/D converters.
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