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HIP7010 - J1850 Byte Level Interface Circuit

General Description

The Intersil HIP7010, J1850 Byte Level Interface Circuit, is a member of the Intersil family of low-cost multiplexed wiring ICs.

Key Features

  • Fully Supports VPW (Variable Pulse Width) Messaging Practices of SAE J1850 Standard for Class B Data Communications Network Interface - 3-Wire, High-Speed, Synchronous, Serial Interface.
  • Reduces Wiring Overhead.
  • Directly Interfaces with 68HC05 and 68HC11 Style SPI Ports.
  • 1MHz, 8-Bit Transfers Between Host and HIP7010 Minimize Host Service Requirements.
  • Automatically Transmits Properly Framed Messages.
  • Prepends SOF to First Byte and Appends C.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HIP7010 ADVANCE INFORMATION August 1996 J1850 Byte Level Interface Circuit Description The Intersil HIP7010, J1850 Byte Level Interface Circuit, is a member of the Intersil family of low-cost multiplexed wiring ICs. The integrated functions of the HIP7010 provide the system designer with components key to building a “Class B” multiplexed communications network interface, which fully conforms to the VPW Multiplexed Wiring protocol specified in the SAE J1850 Standard. The HIP7010 is designed to interface with a wide variety of Host microcontrollers via a standard three wire, high-speed (1MHz), synchronous, serial interface. The HIP7010 automatically produces properly framed VPW messages, prepending the Start of Frame (SOF) symbol and calculating and appending the CRC check byte.