HIP7030A2 Description
The HIP7030A2 HCMOS Microputer is a member of the CDP68HC05 family of low-cost single-chip microputers. The integrated hardware functions provide the system designer with a plete set of building blocks for implementing a “Class B” multiplexed munications network interface, which fully conforms to the VPW Multiplexed Wiring protocol specified in SAE Remended Practice J1850. This 8-bit microputer unit (MCU) contains an...
HIP7030A2 Key Features
- Fully Supports VPW Specifications of SAE J1850 Standard for Class B Data munications Network Interface
- On-Chip Memory
- 176 Bytes of RAM
- 2110 Bytes of User ROM
- 13 Bidirectional I/O Lines
- 16-Bit Timer with Capture and pare Registers
- Serial Peripheral Interface (SPI) System
- Watchdog Timer and Slow Clock Detect
- 10MHz Operating Frequency (5.0MHz Internal Bus Frequency) at 5V
- Built-In-Test Bootstrap Mode with 242 Bytes of ROM