Overview: TM ISL6440A
Data Sheet October 2001 File Number 9041 Advanced PWM and Triple Linear Power Controller for Gateway Applications
The ISL6440A provides the power control and protection for four output voltages required by microprocessors used in high-performance, graphics-intensive gateway applications. The IC integrates a voltage-mode PWM controller and three linear controllers, as well as the monitoring and protection functions into a 28 lead SOIC package. The synchronous rectified buck converter includes an Intel®patible, TTL five-input, digital-to-analog converter (DAC) that adjusts the core PWM output voltage from 1.3VDC to 2.05VDC in 0.05V steps and from 2.1V DC to 3.5VDC in 0.1V increments. The precision reference and voltage-mode control provide ±1% static regulation. A TTL-patible signal applied to the SELECT pin dictates which method of control is used for the AGP bus power. A low state results in linear control of the AGP bus to 1.5V, while a high state transitions the output through a linearly controlled soft-start to 3.3V, followed by full enhancement of the external MOSFET to pass the input voltage. The other two linear regulators provide fixed output voltages of 1.5V GTL bus power and 1.8V power for the north/south bridge core and/or cache memory. These levels are user-adjustable by means of an external resistor divider and pulling the FIX pin low. All linear controllers can employ either N-Channel MOSFETs or bipolar NPNs for the pass transistor. The ISL6440A monitors all the output voltages. A single power good signal is issued when the core is within ±10% of the DAC setting and all other outputs are above their undervoltage levels. Additional built-in overvoltage protection for the core output uses the lower MOSFET to prevent output voltages above 115% of the DAC setting. The PWM controller’s overcurrent function monitors the output current by using the voltage drop across the upper MOSFET’s rDS(ON).
