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CD40101BMS - CMOS 9-Bit Parity Generator/Checker

General Description

The CD40101BMS is a 9-bit (8 data bits plus 1 parity bit) parity generator/checker.

It may be used to detect errors in data transmission or data retrieval.

Odd and even outputs facilitate odd or even parity generation and checking.

Key Features

  • Pinout.
  • High Voltage Type (20V Rating).
  • 100% Tested for Quiescent Current at 20V CD40101BMS TOP VIEW.
  • 5V, 10V and 15V Parametric Ratings.
  • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC.
  • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V.
  • Standardized Symmetrical Output Characteristics D1 1 D2 2 D3 3 D4 4 D9 5 ODD OUT 6 VSS 7 14 VDD 13.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CD40101BMS December 1992 CMOS 9-Bit Parity Generator/Checker Features Pinout • High Voltage Type (20V Rating) • 100% Tested for Quiescent Current at 20V CD40101BMS TOP VIEW • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Standardized Symmetrical Output Characteristics D1 1 D2 2 D3 3 D4 4 D9 5 ODD OUT 6 VSS 7 14 VDD 13 D8 12 D7 11 D6 10 D5 9 EVEN OUT 8 INHIBIT • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Description The CD40101BMS is a 9-bit (8 data bits plus 1 parity bit) parity generator/checker.