Datasheet Summary
April 1995
Radiation Hardened Dual 4-Input NAND Gate
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T14, LEAD FINISH C TOP VIEW
A1 1 B1 2 NC 3 C1 4 D1 5 Y1 6 GND 7 14 VCC 13 D2 12 C2 11 NC 10 B2 9 A2 8 Y2
Features
- 1.25 Micron Radiation Hardened SOS CMOS
- Total Dose 300K RAD (Si)
- Single Event Upset (SEU) Immunity <1 x 10-10 Errors/Bit-Day (Typ)
- SEU LET Threshold >80 MEV-cm2/mg
- Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse
- Latch-Up Free Under Any Conditions
- Military Temperature Range: -55oC to +125oC
- Significant Power Reduction pared to ALSTTL Logic
- DC Operating Voltage Range: 4.5V to 5.5V
- Input Logic Levels
- VIL = 30% of VCC Max
- VIH =...