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TECHNICAL DATA
KK4021B
8-Bit Shift Register
High-Voltage Silicon-Gate CMOS
The KK4021B is an Edge-Triggered 8-Bit Shift Register (Parallel-toSerial Converter) with a synchronous Serial Data Input (DS), a Clock Input (CP), an asynchronous active HIGH Parallel Load Input (PL), eight asynchronous Parallel Data Inputs (P0-P7) and Buffered Parallel Outputs from the last three stages (Q5-Q7). Information on the Parallel Data Inputs (P0-P7) is asynchronously loaded into the register while the Parallel Load Input (PL) is HIGH, independent of the Clock (CP) and Serial Data (DS) inputs. Data present in the register is stored on the HIGH-to-LOW transition of the Parallel Load Input (PL).
KK4021B Datasheet
