KK74AC175 Datasheet | Kodenshi AUK Group

TECHNICAL DATA .. Quad D Flip-Flop with mon Clock and Reset High-Speed Silicon-Gate CMOS The KK74AC175 is identical in pinout to the LS/ALS175, HC/HCT175. The device inputs are patible with standard CMOS outputs; with pullup resistors, they are patible with LS/ALS outputs. This device consists of four D flip-flops with mon Reset and Clock inputs, and separate D inputs. Reset (active-low) is asynchronous and occurs when a low level is applied to the Reset input. Information at a D input is transferred to the corresponding Q output on the next positivegoing edge of the Clock input. - Outputs Directly Interface to CMOS, NMOS, and TTL - Operating Voltage Range: 2.0 to 6.0 V - Low Input Current: 1.0 µA; 0.1 µA @ 25°C - High Noise Immunity Characteristic of CMOS Devices - Outputs Source/Sink 24 m A ORDERING INFORMATION KK74AC175N Plastic KK74AC175D SOIC TA = -40° to 85° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Reset PIN 16=VCC PIN 8 = GND L H H H X = Don’t care L Clock X D X H L X Outputs Q L H L Q H L H no change .. MAXIMUM RATINGS- Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL - Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 ±20 ±50 ±50 750 500 -65 to +150 260 Unit V V V m A m A m A m W °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Remended Operating Conditions. +Derating - Plastic DIP: - 10 m W/°C from 65° to 125°C SOIC Package: : - 7 m W/°C from 65° to 125°C REMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TJ TA IOH IOL tr, tf Parameter DC...